Delay fault coverage, test set size, and performance trade-offs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay variation tolerance for domino circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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It is widely believed that any true (or sensitizable) critical path of length ≥ T must be sped up in order for a circuit to have a delay T. In this paper I demonstrate that this notion is pessimistic. Many true paths can never affect the delay of the circuit — whenever such a path propagates a signal, some other path that is at least as long also propagates a signal.The theory for a new classification of paths based on the impact on the circuit delay is presented and conditions are given under which a path (or a set of paths) must be sped up in order to improve the circuit delay. The conditions for the categorization are independent of the delays in the circuit and are valid for all delay assignments.This work indicates that the widely employed notions of true and false paths may be misleading both for timing optimization and delay analysis of logic circuits.