Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A new delay test based on delay defect detection within slack intervals (DDSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Small-delay-fault ATPG with waveform accuracy
Proceedings of the International Conference on Computer-Aided Design
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This paper addresses the problem of obtaining accurate fault coverages for the gate delay fault model. For a gate delay fault, it is not sufficient to only find a test. One also has to accurately determine the size of the fault detected. We first show that previous methodologies for determining gate delay fault coverages have certain limitations. A method is then investigated to determine all the possible ranges of detected fault sizes, using the traditional fixed sampling time approach. However, with the constraints of a realistic inertial delay model, it is then shown that it might still not be possible to achieve the coverages required to guarantee circuit operation without malfunctions. A new and more realistic delay model is proposed to obtain true fault coverages that extend up to the actual circuit slacks whenever possible. An alternate test application strategy, involving the usage of varying sampling times, is also proposed to further enhance the actual fault coverages obtained under the proposed delay model. Results of experiments performed to evaluate these methods are given