Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
Resistance Characterization for Weak Open Defects
IEEE Design & Test
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
False write through and un-restored write electrical level fault models for SRAMs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
Integration of Non-Classical Faults in Standard March Tests
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Functional Memory Faults: A Formal Notation and a Taxonomy
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Importance of Dynamic Faults for New SRAM Technologies
ETW '03 Proceedings of the 8th IEEE European Test Workshop
March iC-: An Improved Version of March C- for ADOFs Detection
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Dynamic Read Destructive Fault in Embedded-SRAMs: Analysis and March Test Solution
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Analysis of resistive-open defects in SRAM sense amplifiers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present an exhaustive study on the influence of resistive-open defects in pre-charge circuits of SRAM memories. In SRAM memories, the pre-charge circuits operate the pre-charge and equalization at a certain voltage level, in general Vdd, of all the couples of bit lines of the memory array. This action is essential in order to ensure correct read operations. We have analyzed the impact of resistive-opens placed in different locations of these circuits. Each defect studied in this paper disturbs the pre-charge circuit in a different way and for different resistive ranges, but the produced effect on the normal memory action is always the perturbation of the read operations. This faulty behavior can be modeled by Un-Restored Write Faults (URWFs) and Un-Restored Read Faults (URRFs), because there is an incorrect pre-charge/equalization of the bit lines after a write or read operation that disturbs the following read operation. In the last part of the paper, we demonstrate that the test of URWFs is more effective in terms of resistive defect detection than that of URRFs and we list the necessary test conditions to detect them.