Test generation for MOS circuits using D-algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets
IEEE Transactions on Computers
Fault Diagnosis of MOS Combinational Networks
IEEE Transactions on Computers
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
IEEE Transactions on Computers
IEEE Transactions on Computers
Diagnosis of Short-Circuit Faults in Combinational Circuits
IEEE Transactions on Computers
Syndrome-Testability Can be Achieved by Circuit Modification
IEEE Transactions on Computers
Syndrome-Testing of " Syndrome-Untestable" Combinational Circuits
IEEE Transactions on Computers
Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks
IEEE Transactions on Computers
Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results
IEEE Transactions on Computers
A Practical Approach to Fault Detection in Combinational Networks
IEEE Transactions on Computers
The Weighted Syndrome Sums Approach to VLSI Testing
IEEE Transactions on Computers
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The challenging problem of logical modeling of physical failures in nMOS LSI/VLSI circuits, and their detection have been considered in this paper from a completely new angle. It has been shown that in a MOS complex cell consisting of series-parallel connections of FET's, any physical failure like 'opens' and' shorts' can be modeled by bridging faults in its equivalent logic circuit. The problem of designing syndrome testable MOS networks at LSI/VLSI level for detection of all types of 'physical failures' is also considered, unlike other existing syndrome testable designs which so far have only aimed at detecting logical failures, i.e., stuck-at [1], [4], or bridging faults [6] in the logic-description of the circuits. Unfortunately, due to the nonexistence of one to one correspondence in between the physical failures and the logical fault models in MQS circuits. all those earlier methods could not be applied with full confidence in a realistic environment. In this paper, we have shown that the MOS networks, properly designed with complex cells, not necessarily in series-parallel form, can exhibit inherent syndrome testability against all physical faults like opens and shorts amongst interconnection lines, irrespective of their logical modeling. The design will be very convenient for easily performing built-in tests (BIT) in LSI/VLSI circuits.