Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers
An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits
IEEE Transactions on Computers
Detection of Multiple Faults in Combinational Logic Networks
IEEE Transactions on Computers
Fault Diagnosis of MOS Combinational Networks
IEEE Transactions on Computers
Sequential Fault Diagnosis in Combinational Networks
IEEE Transactions on Computers
Generic Fault Characterizations for Table Look-Up Coverage Bounding
IEEE Transactions on Computers
On Combinational Networks with Restricted Fan-Out
IEEE Transactions on Computers
A Wire-Routing Scheme Based on Trunk-Division Methods
IEEE Transactions on Computers
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
IEEE Transactions on Computers
A Practical Approach to Fault Detection in Combinational Networks
IEEE Transactions on Computers
Spectral Fault Signatures for Internally Unate Combinational Networks
IEEE Transactions on Computers
Fault Diagnosis in Combinational Tree Networks
IEEE Transactions on Computers
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In this paper, we are concerned with the problem of generating minimal fault-detection experiments for fanout-free combinational logic networks. We establish the greatest lower bound on the necessary number of fault-detecting tests and show in a systematic way how such experiments can be obtained.