Multiple-Fault Detection and Location in Fan-Out Free Combinational Circuits
IEEE Transactions on Computers
Multiple Fault Detection for Combinational Logic Circuits
IEEE Transactions on Computers
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines
IEEE Transactions on Computers
On-Line Diagnosis of Unrestricted Faults
IEEE Transactions on Computers
Efficient Design of Self-Checking Checker for any m-Out-of-n Code
IEEE Transactions on Computers
Strongly Fault Secure Logic Networks
IEEE Transactions on Computers
Partially Self-Checking Circuits and Their Use in Performing Logical Operations
IEEE Transactions on Computers
On the Design of Logic Networks with Redundancy and Testability Considerations
IEEE Transactions on Computers
On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests
IEEE Transactions on Computers
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers
| Hi-index | 14.98 |
All the totally self checking (TSC) circuits known so far [3]-[8] restrict their fault sets to either single or multiple but unidirectional stuck-at faults. Meyer and Sundstrom [20] have considered on line diagnosis of unrestricted faults but the class of circuits proposed by them does not fall under the category of TSC circuits. This paper proposes a new type of circuit model which is TSC for a fault set, consisting of all possible, i.e., unrestricted stuck-at faults on all the gate input and output signal lines. The model uses redundancy in both space and time domains and realizes combinatorial functions. Some important properties of the model are brought out by a set of lemmas and theorems. The viability of the model is demonstrated by a circuit example which uses CMOS technology.