Multiple-Fault Detection and Location in Fan-Out Free Combinational Circuits

Authors:
G. Fantauzzi;A. Marsella
Affiliations:
Società Italiana Telecomunicazioni Siemens;-
Venue:
IEEE Transactions on Computers
Year:
1974

Citing 3
Cited 2

A Nand Model ror Fault Diagnosis in Combinational Logic Networks

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Fault location in cellular arrays

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Multiple Fault Detection for Combinational Logic Circuits

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Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains

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Abstract

Two algorithms are presented for the detection and location of single or multiple stuck faults in a fan-out free combinational circuit. The algorithms are based on a canonic representation of the indistinguishability classes of faults. The number of tests required in these algorithms are shown to be a linear function of the number of gates in the circuit.