Design of test pattern generators for built-in test

Authors:
Ramaswami Dandapani;Janak H. Patel;Jacob A. Abraham
Affiliations:
Coordinated Science Laboratory, University of Illinois, Urbana, Illinois;Coordinated Science Laboratory, University of Illinois, Urbana, Illinois;Coordinated Science Laboratory, University of Illinois, Urbana, Illinois
Venue:
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Year:
1984

Citing 3
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Abstract

This paper presents methods for designing cost-effective on-chip built-in test generators. Given an unordered test set, these methods produce an area and time efficient generator circuit using a small ROM and some additional logic. Some simulation results are presented.