A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks
IEEE Transactions on Computers
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Implicit test pattern generation constrained to cellular automata embedding
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Design of test pattern generators for built-in test
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
| Hi-index | 14.98 |
Currently proposed and used schemes for built-in testing (B-I-T) use as test generators either binary counters (exhaustive testing), linear feedback shift registers (semiexhaustive testing), or ROM's containing the test vectors (prestored testing). The disadvantages of these methods have been discussed in [4], and a store-and-generate B-I-T arrangement was proposed as a compromise between the exhaustive and the prestored form of test generation. Unfortunately, no systematic method was given for producing tests.