Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Aliasing errors in linear automata used as multiple-input signature analyzers
IBM Journal of Research and Development
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
A Probabilistic Analysis of Test Response Compaction
A Probabilistic Analysis of Test Response Compaction
Structured Logic Testing
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Automated synthesis of phase shifters for built-in self-test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Originally developed decades ago, logic built-in self-test(BIST) evolved and is now increasingly being adopted tocope with rapid growth in design size and complexity. Comparedto deterministic pattern test, logic BIST requiresmany more test patterns, and therefore, increased test timeunless many more internal scan chains can be shifted in parallel.To match this large number of scan chains, the widthof the signature analyzer would have to be enlarged, whichwould result in large area overhead and signature storagespace. Instead, a combinational space-compactor isinserted between the scan chain outputs and the signatureanalyzer inputs. However, the compactor may deterioratethe ability to test and diagnose the design. This paper analyzeshow compactors affect test and diagnosis and showsthat compactors can be designed to actually improve thetestability of certain faults, while providing full diagnosiscapability. Algorithms that allow automated design of optimalcompactors are presented and results are discussed.