IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Parallel Random Number Generation for VLSI Systems Using Cellular Automata
IEEE Transactions on Computers
Two-level coding for error control in magnetic disk storage products
IBM Journal of Research and Development
Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Probability and Statistics with Reliability, Queuing and Computer Science Applications
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A new and effective pseudo-random test pattern generator, termed GLFSR, is introduced. These are linear feedback shift registers over a Galois field GF(2δ), (δ 1). Unlike conventional LFSRs, which are over GF(2), these generators are not equivalent to cellular arrays, and are shown to achieve significantly higher fault coverage. Experimental results are presented in this paper depicting that the proposed GLFSR can attain fault coverage equivalent to the LFSR, but with significantly fewer patterns. Specifically, results obtained demonstrate that in combinational circuits, for both stuck-at as well as transition faults, the proposed GLFSR outperforms all conventional pattern generators. Moreover, these experimental results are validated by ctrtain randomness tests which demonstrate that the patterns generated by GLFSR achieve a higher degree of randomness.