IEEE Transactions on Computers
Shift Register Sequences
Fault coverage of a long random test sequence estimated from a short simulation
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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Test-pattern generation for high fault coverage is an expensive and time-consuming process. As an alternative circuits can be tested by applying random or pseudorandom patterns. To analyze random testing without fault simulation, the number of vectors that detect a fault in each fault class must be enumerated. A fault-detection function whose number of minterms is identical to the fault detectability is constructed. Extensions are made to the Cutting algorithm to evaluate the signal probability of the detection or its bounding functions. The signal probability can then be converted easily into an exact detectability or narrow detectability range associated with each fault.