The Total Delay Fault Model and Statistical Delay Fault Coverage
IEEE Transactions on Computers
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
IEEE Transactions on Computers
Delay Fault Coverage Enhancement Using Variable Observation Times
Journal of Electronic Testing: Theory and Applications
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Memory Efficient ATPG for Path Delay Faults
ATS '97 Proceedings of the 6th Asian Test Symposium
An Analytical Delay Model Based on Boolean Process
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Selection of Crosstalk-Induced Faults in Enhanced Delay Test
Journal of Electronic Testing: Theory and Applications
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Delay testing is important for high speed ICs. The main difficulty in delay testing comes from the huge number of paths and the large percentage of delay untestable paths. Therefore, it is critical to reduce the number of paths to be tested in delay testing. This paper presents two approaches to delay testing with significant reduction of number of paths to be tested, which provide high path delay fault coverage by testing a small number of paths. In the first approach, it is necessary to sample the primary output twice, one before and another after the transition for each test pair. The second approach is by means of accurate measurement of delays of very limited number of paths. In order to make this approach feasible, the paper also introduces a new concept of path sensitization, termed single-transition sensitization, to allow direct measurement of propagation delay of those paths. The paper presents how to select the very limited number of paths, termed sample paths, and how to generate test pairs and observation times for the sample paths for the first approach. On the other hand, it is noted for the second approach that under the analytical delay model (Proc. 9th International Conf. on VLSI Design, Bangalore, India, Jan. 1996, pp. 162–165), most of the paths are delay testable, which makes the accurate measurement approach feasible. In fact, it would be very difficult to select sample paths based on single path sensitization as it was done in (IEEE Trans. on Computers, Vol. c-29, No. 3, pp. 235–248, March 1980). The paper shows that the number of sample paths is linear to the number of gates in the circuit under test, despite exponential growth in the number of single paths.