Cellular Logic-in-Memory Arrays
IEEE Transactions on Computers
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Testable Sequential Cellular Arrays
IEEE Transactions on Computers
Hi-index | 14.98 |
This paper introduces procedures which enable one to settle the tessellation problem for the class of combinational cellular arrays with each cell having a binary horizontal input and a binary vertical input. Where all input combinations are applicable to all cells in the array in this class, the necessary number of tests is obtained from necessary prime as well as composite tessellations.