A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Combinatorial Algorithms: Theory and Practice
Combinatorial Algorithms: Theory and Practice
| Hi-index | 14.98 |
A formal approach to the analysis of a combinational circuit described at the high level is presented. It produces information conducive to the acceleration of test generation algorithms. This analysis yields, as its main product, information which can be used to reduce the amount of effort expended during backtracing, by guiding this process towards decisions (assignments) less likely to cause conflicts and minimizing the amount of work between backtracks. RIDDLE, an algorithm which performs this analysis in time linear in the number of signals, is introduced. Experimental results for the special case of combinational gate-level designs are also given.