A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Combinatorial Algorithms: Theory and Practice
Combinatorial Algorithms: Theory and Practice
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
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We present a formal approach to the analysis of combinatorial gatelevel designs, which produces information conducive to the acceleration of test generation algorithms. This analysis yields as its main product, information which can be used to reduce the amount of effort expended during backtracing, by guiding this process towards decisions (assignments) less likely to cause conflicts, and minimizing the amount of work between backtracks. We introduce the G-RIDDLE approach for performing this analysis, as a refinement of the more general case which handles designs consisting of multi-input/ multi-output combinatorial blocks. Experimental results are given for a popular benchmark of combinatorial gate level designs.