A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Hi-index | 0.00 |
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The advantages gained by the proposed partitioning method are based on the increase in the number of dominators in the circuit graph. In contrast to conventional ATPG working on the unpartitioned circuit test generation is less time consuming now and redundancies can often be identified without any backtracks. Experimental results illustrate the superiority of the cone oriented partitioning approach. Independent of the underlying ATPG algorithm the cone oriented partitioning results on average in a performance increase by more than a factor of 2.