Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count
Journal of Computer Science and Technology
Syndrome signature in output compaction for VLSI BIST
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Performance-driven technology mapping with MSG partition and selective gate duplication
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 14.98 |
The parity testability of a single output is related to its partition in terms of maximal supergates, and a scheme is proposed for making an untestable circuit parity testable by augmenting its maximal supergates. Only a small amount of extra logic and a single external test-mode pin are required to complete the design. The test procedure is simple, and the hardware overhead is low.