A 65nm flash-based FPGA fabric optimized for low cost and power

Authors:
Jonathan Greene;Sinan Kaptanoglu;Wenyi Feng;Volker Hecht;Joel Landry;Fei Li;Anton Krouglyanskiy;Mihai Morosan;Val Pevzner
Affiliations:
Microsemi Corporation SOC Products Group, Mountain View, CA, USA;Microsemi Corporation SOC Products Group, Mountain View, CA, USA;Microsemi Corporation SOC Products Group, Mountain View, CA, USA;Microsemi Corporation SOC Products Group, Mountain View, CA, USA;Microsemi Corporation SOC Products Group, Mountain View, CA, USA;Microsemi Corporation SOC Products Group, Mountain View, CA, USA;Microsemi Corporation SOC Products Group, Mountain View, CA, USA;Microsemi Corporation SOC Products Group, Mountain View, CA, USA;Microsemi Corporation SOC Products Group, Mountain View, CA, USA
Venue:
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Year:
2011

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Abstract

This paper describes a non-volatile reprogrammable FPGA fabric, whose configuration data are provided directly by flash memory. The fabric is optimized for low-cost, low-power applications, leveraging the density of flash and the elimination of conventional configuration SRAM and its attendant static power. After surveying the necessary background on flash and its application to FPGAs, the 1T flash cell is described along with relevant novel aspects of the fabric architecture. The addition of a third level of switching between inter-cluster signals and logic inputs helps to reduce area and raise typical utilization above 95%. Despite the longer signal path, performance is maintained by synergism between the improved routing flexibility and extreme minimization of the fastest LUT input delay. Test cost is reduced by built-in circuits that can test all switches without reprogramming the flash memory. The fabric has been implemented in a 65nm CMOS embedded flash process.