Static scheduling of multi-domain memories for functional verification
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Power-aware RAM mapping for FPGA embedded memory blocks
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
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We present techniques for generating addresses for memories containing multiple arrays. Because these techniques rely on the inversion or rearrangement of address bits, they are faster and require less hardware to compute than the traditional technique of addition. Use of these techniques can improve performance and cost of application-specific memory subsystems by decreasing effective access time to arrays and by reducing address generation hardware. The primary drawback to this approach is that extra memory space is occasionally required, but in over a million tested cases, this extra memory space is on average only 2% and no worse than 17.4% of the utilized memory space. This amount of wasted address space is significantly less than the amount required by the only known similar technique and rarely necessitates the allocation of additional memory components. These techniques provide a foundation for adder-free address generation for manually and automatically generated application-specific memory designs