Virtual Page Tag Reduction for Low-power TLBs

Authors:
Peter Petrov;Alex Orailoglu
Affiliations:
-;-
Venue:
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Year:
2003

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Abstract

We present a methodology for a power-optimized, software-controlledTranslation Lookaside Buffer (TLB) organization. A highly reducednumber of Virtual Page Number (VPN) bits sufficient to performphysical address translation is efficiently identified and usedwhen performing TLB lookups, delivering significant powerreductions. Information regarding the virtual address space of theprogram code and data provided by the compiler is augmented withinformation regarding the dynamically linked libraries and dataallocated run-time by the loader, the dynamic linker, and thememory manager. The hardware support needed is constrained todisabling bitlines of the tag arrays associated to the I-TLB andthe D-TLB. Algorithms for identifying the reduced VPNs for poweroptimized TLB operations together with the required OS support arepresented.