Proceedings of the 2003 international symposium on Low power electronics and design
Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Floorplanning for 3-D VLSI design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Register binding for clock period minimization
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This paper presents a integer linear programming-based approach which assigns the given modules to a set of layers for the three-dimensional floorplanner. The objective is to minimize the chip area which is the maximum layer area among the set of threedimensional integrated circuits. We first formulate the module assignment which automatically determines the given modules to a set of three-dimensional layers. It means that a set of partitioned results are constructed for a three-dimensional floorplanner. Furthermore, a simulated-annealing-(SA for short)based floorplanner which applied the sequence-pair to perturb the relationships of modules is used to obtain the floorplan for each layer in three-dimensional architecture. Experimental results show that the maximum chip area can be minimized by the integer linear programming-based approach. One well-developed floorplanner can obtain a feasible floorplan with the minimization area for three-dimensional architecture.