Sleep transistor sizing using timing criticality and temporal currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A fact that has generally been unnoticed is that sleep transistors for leakage reduction can significantly damp the resonant supply noise due to their series resistance. This paper describes an optimal sleep transistor sizing method considering the dominant resonant supply noise. We show that a smaller sleep transistor can offer a smaller worst case supply noise due to the increased damping. We also propose an adaptive sleep transistor technique which automatically dampens the resonant noise only when it is detected. Simulations in 32nm CMOS show that the resonant noise is reduced by 32% using the proposed technique.