Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Buffered Clock Tree for High Quality IC Design
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Ispd2009 clock network synthesis contest
Proceedings of the 2009 international symposium on Physical design
Exact route matching algorithms for analog and mixed signal integrated circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Fast timing-model independent buffered clock-tree synthesis
Proceedings of the 47th Design Automation Conference
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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It is important for a synchronous design to minimize the clock skew in a clock tree. In this paper, based on the length-matching benefit in exact routing, an efficient four-stage algorithm is further proposed to generate a symmetrical buffered clock tree with smaller clock skew under a given slew-rate constraint. For symmetrical buffered clock routing, compared with Shih's approach, the experimental results show that our proposed approach can use extra 2.54% of total resource to reduce 85.78% of clock skew in a symmetrical buffered clock tree with satisfying the slew-rate constraint for tested benchmarks in less CPU time on the average.