A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes

Authors:
Shanq-Jang Ruan;Tsang-Chi Kan;Jih-Chieh Hsu
Affiliations:
National Taiwan University of Science and Technology, Taipei, Taiwan Roc;National Taiwan University of Science and Technology, Taipei, Taiwan Roc;National Taiwan University of Science and Technology, Taipei, Taiwan Roc
Venue:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Year:
2010

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Abstract

As the process technology advances, not only capacitive but also inductive effect is considered for bus encoding. However, most existing coding techniques only consider power or delay reduction based on either the RC or RLC model. This is due to the fact that the variation of power is hard to generalize together with noise and delay by using the RLC model. In this paper, we first show the growth and decline of power and noise behaviors while considering the RLC effect. According to the observations, we devise a quantitative cost function, which adopts the priority between capacitive and inductive effects on trade-off between power and noise. Based on the cost function, we then propose an invert-base bus encoding scheme to reduce power, noise, and delay simultaneously. Experimental results show that power, noise, and delay reductions by using our scheme are up to 19.97%, 14.73%, and 17.70% respectively for an 8-bit bus.