Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme

Authors:
K S. Sainarayanan;C Raghunandan;M B. Srinivas
Affiliations:
International Institute of Information Technology (IIIT), Hyderabad, India;International Institute of Information Technology (IIIT), Hyderabad, India;International Institute of Information Technology (IIIT), Hyderabad, India
Venue:
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Year:
2007

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Abstract

The Scalable Communications Core (SCC) is a power- and area-efficient solution for physical layer (PHY) and lower MAC processing of concurrent multiple wireless protocols. Our architecture consists of coarse-grained, heterogeneous, programmable accelerators ...