Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses

  • Authors:
  • JIANGJIANG LIU;NIHAR R. MAHAPATRA;KRISHNAN SUNDARESAN

  • Affiliations:
  • -;-;-

  • Venue:
  • ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
  • Year:
  • 2003

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Abstract

Communication components (address, instruction, anddata buses and associated hardware like I/O pins, pads,and buffers) are contributing increasingly to the area/costand power consumption of microprocessor systems. To decreasecosts due to address buses, we propose to use narrowwidths for underutilized buses (hardware-only compression)to transmit information in multiple cycles. Weanalyze performance and power consumption overheadsof hardware-only compression and investigate the use of"address concatenation" to mitigate performance loss andaddress offsets and XORs to reduce power consumptionoverheads.