Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partial bus-invert coding for power optimization of system level bus
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Synthesis of low-overhead interfaces for power-efficient communication over wide buses
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
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In this paper, an approach to the implementation of digital systems is presented which utilizes dynamic hardware reconfiguration in order to automatically minimize the power dissipated on module interconnections such as system buses during system run time. Reduction of power dissipation is achieved by means of an activity-reducing system bus encoding technique. Encoder and decoder are implemented with dynamically reconfigured code tables which contain a transition minimizing code that is periodically recomputed during run time of the system in order to adapt to variations in the statistical parameters of the encoded data stream. We present the theoretical basics and an efficient implementation of a corresponding coder-decoder system. Experimental results showed a reduction in bus transition activity of up to 41%.