Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Low-power current-mode transceiver for on-chip bidirectional buses
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
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In this paper, we present high-performance bidirectional repeaters that recondition the signal waveform and reduce the signal degradation. We also present the application of these repeaters to the design of high-performance bidirectional busses. SPICE simulation results for long bidirectional interconnects show an almost linear increase in delay with repeaters compared to a quadratic increase in delay without repeaters. These repeaters are also applied to improve the performance of long AND domino gates. SPICE simulation results show a significant reduction in the delay of long AND domino gate with repeaters.