Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
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Future Multiprocessor Systems-on-Chip (SoCs) will consist of various digital and analog components, such as processing cores, storage elements, customized IP-cores, analog peripheral devices, and many other items of MEMS. Network-on-chip is a promising mechanism which provides a power- and performance-efficient communication infrastructure for such complex on-chip systems. This paper presents a routing algorithm to cope with the dynamic traffic pattern of network-on-chip (NoC) architectures aiming to distribute the on-chip traffic evenly across the network. In this algorithm, instead of relying solely on local congestion information, the routes are determined based on the global traffic information. This is achieved by employing a light-weight and efficient control network which monitors the on-chip traffic and collects the required global information for determining the appropriate paths between any pairs of communicating nodes in such a way that the congestion is avoided and the NoC load is balanced. Our experiments show that the proposed method outperforms the conventional deterministic and adaptive routing mechanisms under some benchmarks running on a 7脳7 NoC.