Fault-Tolerant Routing Schemes in RDT(2,2,1)/a-Based Interconnection Network for Networks-on-Chip Designs

Authors:
Mei Yang;Yingtao Jiang;Tao Li;Yulu Yang
Affiliations:
University of Nevada, Las Vegas;University of Nevada, Las Vegas;Nankai University, China;Nankai University, China
Venue:
ISPAN '05 Proceedings of the 8th International Symposium on Parallel Architectures,Algorithms and Networks
Year:
2005

Citing 0
Cited 2

Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Networks on chips: structure and design methodologies

Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies

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Abstract

It has been well recognized that the fault-tolerance capability is vital for a NoC system, since one faulty link/processor may isolate a large fraction of processors. Continuing from a previous paper [13] where a RDT(2,2,1)/..-based interconnection network for NoC designs was proposed, in this paper, we investigate fault-tolerant routing schemes on NoC systems featuring a RDT-based interconnection network. In specific, we propose two fault-tolerant routing schemes in the presence of either single link/node failure or multiple link/node failures. The proposed routing schemes are based on deterministic routing. Alternative routes are discovered by properly selecting the intermediate nodes between the source and the destination nodes on the rank tori. As of the single link/node failure case, we show that the number of routers on the detoured route generated by the proposed routing scheme is at most 2 more than the number of routers on the original route.