Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Towards Open Network-on-Chip Benchmarks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
State observer controller design for packets flow control in networks-on-chip
The Journal of Supercomputing
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The performance analysis and comparison of 2x4 network on chip (NoC) topology are mainly presented in this paper. Firstly, three common 2x4 topologies, 2D Mesh topology, 2D Torus topology and hierarchical Mesh topology are designed. Secondly, the performances of three topologies are analyzed and compared in detail by using NoC performance evaluation standard. Finally, the occupying resources of three topologies are also compared. The result shows that 2D Torus topology can achieve higher throughput and lower average network latency in occupying fewer resources.