A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Networks on chip
A holistic methodology for network processor design
LCN '03 Proceedings of the 28th Annual IEEE International Conference on Local Computer Networks
Feedback driven instruction-set extension
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Network Application Driven Instruction Set Extensions for Embedded Processing Clusters
PARELEC '04 Proceedings of the international conference on Parallel Computing in Electrical Engineering
Resource efficiency of the GigaNetIC chip multiprocessor architecture
Journal of Systems Architecture: the EUROMICRO Journal
A multiprocessor cache for massively parallel soc architectures
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
Evaluating large system-on-chip on multi-FPGA platform
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
GigaNetIC – a scalable embedded on-chip multiprocessor architecture for network applications
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
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Information processing and networking of technical devices find their way into our daily life. In order to process the continuously growing quantity of data, powerful communication nodes for network processing are needed. We present an architecture for network processors that is based on a uniform, massively parallel structure. Thus, our approach takes advantage of reusing predefined IP building blocks. This leads to a short time to market, a high reliability and a scalable architecture. Our architecture is scalable to different areas of application by varying the number of integrated processors. Additionally, specific hardware accelerators can be embedded, which are optimized for the target application, in order to be especially resource-efficient in respect to power consumption, computational power and required area.