A Scalable Parallel SoC Architecture for Network Processors
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A multiprocessor cache for massively parallel soc architectures
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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The GigaNetIC project aims to develop high-speed componentsfor networking applications based on massivelyparallel architectures. A central part of this project is thedesign, evaluation, and realization of a parameterizablenetwork processing unit. In this paper we present a designmethodology for network processors which encompassesthe research areas from the application software down tothe gate level of the chip. Key components of this holisticapproach have been successfully applied to characteristicexamples of architecture refinements.