Network Application Driven Instruction Set Extensions for Embedded Processing Clusters

Authors:
Matthias Grunewald;Dinh Khoi Le;Uwe Kastens;Jorg-Christian Niemann;Mario Porrmann;Ulrich Ruckert;Adrian Slowik;Michael Thies
Affiliations:
University of Paderborn, Germany;University of Paderborn, Germany;University of Paderborn, Germany;University of Paderborn, Germany;University of Paderborn, Germany;University of Paderborn, Germany;University of Paderborn, Germany;University of Paderborn, Germany
Venue:
PARELEC '04 Proceedings of the international conference on Parallel Computing in Electrical Engineering
Year:
2004

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Abstract

This paper addresses the design automation of instruction set extensions for application-specific processors with emphasis on network processing. Within this domain, increasing performance demands and the ongoing development of network protocols both call for flexible and performance-optimized processors. Our approach represents a holistic methodology for the extension and optimization of a processorýs instruction set. The starting point is a concise yet powerful processor abstraction, which is well suited to automatically generate the important parts of a compiler backend and cycle-accurate simulator so that domain-characteristic benchmarks can be analyzed for frequently occurring instruction pairs. These instruction pairs are promising candidates for the extension of the instruction set by means of super-instructions. Provided that a new super-instruction meets a given performance threshold, a fine-grained performance re-evaluation of the adapted processor design can be conducted instantly. With respect to the chosen domain-characteristic benchmark, the tool-chain pinpoints important characteristics such as execution performance, energy consumption, or chip area of the extended design. Using this holistic design methodology, we are able to judge a refinement of the processor rapidly.