ACM Transactions on Computer Systems (TOCS)
Bit section instruction set extension of ARM for embedded applications
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Flexible Control of Parallelism in a Multiprocessor PC Router
Proceedings of the General Track: 2002 USENIX Annual Technical Conference
Taming the IXP network processor
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Network Application Driven Instruction Set Extensions for Embedded Processing Clusters
PARELEC '04 Proceedings of the international conference on Parallel Computing in Electrical Engineering
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Memory allocation for embedded systems with a compile-time-unknown scratch-pad size
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Overcoming the memory wall in packet processing: hammers or ladders?
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Internet clean-slate design: what and why?
ACM SIGCOMM Computer Communication Review
Evaluating Dynamic Task Mapping in Network Processor Runtime Systems
IEEE Transactions on Parallel and Distributed Systems
On runtime management in multi-core packet processing systems
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Analytic modeling of network processors for parallel workload mapping
ACM Transactions on Embedded Computing Systems (TECS)
Runtime Support for Multicore Packet Processing Systems
IEEE Network: The Magazine of Global Internetworking
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Packet forwarding operations in network systems are often performed in software so that routers can be updated as new protocols and service features are developed. To meet the processing demands of high-performance networks, multiprocessor systems-on-a-chip with dozens of cores are employed to provide raw processing power. Management of these processors and other system resources to achieve high forwarding rates is a key challenge. In particular, the allocation of processing workloads and the placement of data structures in memory have an enormous impact on system performance. Our work proposes a runtime system that manages these system resources. Much related work has proposed the use of cache memory hierarchies in packet processors. In this work, we show that our dynamic placement strategy can outperform a conventional cache memory and achieve up to 1.77 times higher hit rates for small memories, which are typically found in packet processing systems.