Bit section instruction set extension of ARM for embedded applications

  • Authors:

  • Bengu Li;Rajiv Gupta

  • Affiliations:

  • The University of Arizona, Tucson, AZ;The University of Arizona, Tucson, AZ

  • Venue:
  • CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
  • Year:
  • 2002

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Abstract

Programs that manipulate data at subword level, i.e. bit sections within a word, are common place in the embedded domain. Examples of such applications include media processing as well as network processing codes. These applications spend significant amounts of time packing and unpacking narrow width data into memory words. The execution time and memory overhead of packing and unpacking operations can be greatly reduced by providing direct instruction set support for manipulating bit sections.In this paper we present the Bit Section eXtension (BSX) to the ARM instruction set. We selected the ARM processor for this research because it is one of the most popular embedded processor which is also being used as the basis of building many commercial network processing architectures. We present the design of BSX instructions and their encoding into the ARM instruction set. We have incorporated the implementation of BSX into the Simplescalar ARM simulator from Michigan. Results of experiments with programs from various benchmark suites show that by using BSX instructions the total number of instructions executed at runtime by many transformed functions are reduced by 4.26% to 27.27% and their code sizes are reduced by `1.27% to 21.05%.