Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Memory access coalescing: a technique for eliminating redundant memory accesses
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
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MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
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Preference-directed graph coloring
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ARM Architecture Reference Manual
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NetBench: a benchmarking suite for network processors
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CC '02 Proceedings of the 11th International Conference on Compiler Construction
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Register allocation & spilling via graph coloring
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Taming the IXP network processor
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Simple offset assignment in presence of subword data
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure
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Bit level types for high level reasoning
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Optimal bitwise register allocation using integer linear programming
LCPC'06 Proceedings of the 19th international conference on Languages and compilers for parallel computing
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Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis
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Speculative subword register allocation in embedded processors
LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
Enhanced bitwidth-aware register allocation
CC'06 Proceedings of the 15th international conference on Compiler Construction
A framework for end-to-end verification and evaluation of register allocators
SAS'07 Proceedings of the 14th international conference on Static Analysis
Speed and precision in range analysis
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Improved bitwidth-aware variable packing
ACM Transactions on Architecture and Code Optimization (TACO)
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Multimedia and network processing applications make extensive use of subword data. Since registers are capable of holding a full data word, when a subword variable is assigned a register, only part of the register is used. New embedded processors have started supporting instruction sets that allow direct referencing of bit sections within registers and therefore multiple subword variables can be made to simultaneously reside in the same register without hindering accesses to these variables. However, a new register allocation algorithm is needed that is aware of the bitwidths of program variables and is capable of packing multiple subword variables into a single register. This paper presents one such algorithm.The algorithm we propose has two key steps. First, a combination of forward and backward data flow analyses are developed to determine the bitwidths of program variables throughout the program. This analysis is required because the declared bitwidths of variables are often larger than their true bitwidths and moreover the minimal bitwidths of a program variable can vary from one program point to another. Second, a novel interference graph representation is designed to enable support for a fast and highly accurate algorithm for packing of subword variables into a single register. Packing is carried out by a node coalescing phase that precedes the conventional graph coloring phase of register allocation. In contrast to traditional node coalescing, packing coalesces a set of interfering nodes. Our experiments show that our bitwidth aware register allocation algorithm reduces the register requirements by 10\% to 50% over a traditional register allocation algorithm that assigns separate registers to simultaneously live subword variables.