Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems

  • Authors:

  • Eiman Ebrahimi;Chang Joo Lee;Onur Mutlu;Yale N. Patt

  • Affiliations:

  • The University of Texas at Austin, Austin, TX, USA;The University of Texas at Austin, Austin, TX, USA;Carnegie Mellon University , Pittsburgh, PA, USA;The University of Texas at Austin, Austin, TX, USA

  • Venue:
  • Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
  • Year:
  • 2010

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Abstract

Cores in a chip-multiprocessor (CMP) system share multiple hardware resources in the memory subsystem. If resource sharing is unfair, some applications can be delayed significantly while others are unfairly prioritized. Previous research proposed separate fairness mechanisms in each individual resource. Such resource-based fairness mechanisms implemented independently in each resource can make contradictory decisions, leading to low fairness and loss of performance. Therefore, a coordinated mechanism that provides fairness in the entire shared memory system is desirable. This paper proposes a new approach that provides fairness in the entire shared memory system, thereby eliminating the need for and complexity of developing fairness mechanisms for each individual resource. Our technique, Fairness via Source Throttling (FST), estimates the unfairness in the entire shared memory system. If the estimated unfairness is above a threshold set by system software, FST throttles down cores causing unfairness by limiting the number of requests they can inject into the system and the frequency at which they do. As such, our source-based fairness control ensures fairness decisions are made in tandem in the entire memory system. FST also enforces thread priorities/weights, and enables system software to enforce different fairness objectives and fairness-performance tradeoffs in the memory system. Our evaluations show that FST provides the best system fairness and performance compared to four systems with no fairness control and with state-of-the-art fairness mechanisms implemented in both shared caches and memory controllers.