Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler

  • Authors:

  • Alexandra Fedorova;Margo Seltzer;Michael D. Smith

  • Affiliations:

  • Simon Fraser University, Canada;Harvard University, USA;Harvard University, USA

  • Venue:
  • PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
  • Year:
  • 2007

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Abstract

We describe a new operating system scheduling algorithm that improves performance isolation on chip multiprocessors (CMP). Poor performance isolation occurs when an application's performance is determined by the behaviour of its co-runners, i.e., other applications simultaneously running with it. This performance dependency is caused by unfair, corunner- dependent cache allocation on CMPs. Poor performance isolation interferes with the operating system's control over priority enforcement and hinders QoS provisioning. Previous solutions required modifications to the hardware. We present a new software solution. Our cache-fair algorithm ensures that the application runs as quickly as it would under fair cache allocation, regardless of how the cache is actually allocated. If the thread executes fewer instructions per cycle than it would under fair cache allocation, the scheduler increases that thread's CPU timeslice. This way, the thread's overall performance does not suffer because it is allowed to use the CPU longer. We describe our implementation of the algorithm in Solaris^TM 10, and show that it significantly improves performance isolation for SPEC CPU, SPEC JBB and TPC-C.