Process cruise control: event-driven clock scaling for dynamic power management
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
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Scheduling Algorithms for Effective Thread Pairing on Hybrid Multiprocessors
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Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
Task activity vectors: a new metric for temperature-aware scheduling
Proceedings of the 3rd ACM SIGOPS/EuroSys European Conference on Computer Systems 2008
Processor hardware counter statistics as a first-class system resource
HOTOS'07 Proceedings of the 11th USENIX workshop on Hot topics in operating systems
Memory performance attacks: denial of memory service in multi-core systems
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
Resource-conscious scheduling for energy efficiency on multicore processors
Proceedings of the 5th European conference on Computer systems
Dynamic workload characterization for power efficient scheduling on CMP systems
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
An evaluation of per-chip nonuniform frequency scaling on multicores
USENIXATC'10 Proceedings of the 2010 USENIX conference on USENIX annual technical conference
Exploring implicit parallelism in class diagrams
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Future Generation Computer Systems
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Journal of Signal Processing Systems
Analyzing resource interdependencies in multi-core architectures to improve scheduling decisions
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Memory bandwidth is a scarce resource in multicore systems. Scheduling has a dramatic impact on the delay introduced by memory contention, but also on the effectiveness of frequency scaling at saving energy. This paper investigates the cross-effects between tasks running on a multicore system, considering memory contention and the technical constraint of chip-wide frequency and voltage settings. We make the following contributions: 1) We identify the memory characteristics of tasks and sort core-specific runqueues to allow a co-scheduling of tasks with minimal energy delay product. 2) According to the memory characteristics of the workload, we set the frequency for individual chips so that the delay is only marginal. Our evaluation with a Linux implementation running on an Intel quad-core shows that memory-aware scheduling can reduce EDP considerably.