Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs?

  • Authors:

  • Eddy Z. Zhang;Yunlian Jiang;Xipeng Shen

  • Affiliations:

  • The College of William and Mary, Williamsburg, VA, USA;The College of William and Mary, Williamsburg, VA, USA;The College of William and Mary, Williamsburg, VA, USA

  • Venue:
  • Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
  • Year:
  • 2010

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Abstract

Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also results in cache contention. A number of studies have examined the influence of cache sharing on multithreaded applications, but most of them have concentrated on the design or management of shared cache, rather than a systematic measurement of the influence. Consequently, prior measurements have been constrained by the reliance on simulators, the use of out-of-date benchmarks, and the limited coverage of deciding factors. The influence of CMP cache sharing on contemporary multithreaded applications remains preliminarily understood. In this work, we conduct a systematic measurement of the influence on two kinds of commodity CMP machines, using a recently released CMP benchmark suite, PARSEC, with a number of potentially important factors on program, OS, and architecture levels considered. The measurement shows some surprising results. Contrary to commonly perceived importance of cache sharing, neither positive nor negative effects from the cache sharing are significant for most of the program executions, regardless of the types of parallelism, input datasets, architectures, numbers of threads, and assignments of threads to cores. After a detailed analysis, we find that the main reason is the mismatch of current development and compilation of multithreaded applications and CMP architectures. By transforming the programs in a cache-sharing-aware manner, we observe up to 36% performance increase when the threads are placed on cores appropriately.