Performance analysis of SoC architectures based on latency-rate servers

Authors:
Jelte Peter Vink;Kees van Berkel;Pieter van der Wolf
Affiliations:
Eindhoven University of Technology, Eindhoven, the Netherlands;NXP Semiconductors Research, Eindhoven, the Netherlands;NXP Semiconductors Research, Eindhoven, the Netherlands
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2008

Citing 4
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Bounding SDRAM interference: detailed analysis vs. latency-rate analysis

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Abstract

This paper presents a method for static performance analysis of SoC architectures. The method is based on a network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly captured as traffic flows and associated latency constraints. The SoC infrastructure is modeled as a set of LR servers to validate that the worst-case delays in handling the traffic flows meet the latency constraints. A multi-channel DVB-T set-top box case study demonstrates the power of the method. Key architecture choices, such as schedule or interconnect variant, can be varied easily to support exploration of architecture options.