Comparing Simulation Alternatives for High-Level Abstraction Modeling of NIC's Buffer Requirements in a Network Node

Authors:
G. R. Garay;M. Leon;R. Aguilar;V. Alarcon
Affiliations:
-;-;-;-
Venue:
CERMA '10 Proceedings of the 2010 IEEE Electronics, Robotics and Automotive Mechanics Conference
Year:
2010

Citing 0
Cited 1

System performance evaluation by combining RTC and VHDL simulation: A case study on NICs

Journal of Systems Architecture: the EUROMICRO Journal

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Abstract

In this paper we compare nine simulation alternatives which can be used for modeling and analysis the hardware components and processing tasks involved in processing a packet flow entering in a network node. In particular, we focus on the capabilities of these alternatives that can be employed for validating an analytical model based on Real-Time Calculus for the performance evaluation of the NIC’s buffer requirements at high-level abstraction.