Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Resource constrained scheduling of uniform algorithms
Journal of VLSI Signal Processing Systems
Static scheduling algorithms for allocating directed task graphs to multiprocessors
ACM Computing Surveys (CSUR)
IEEE Transactions on Parallel and Distributed Systems
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
An automated exploration framework for FPGA-based soft multiprocessor systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Computers and Operations Research
Allocation and scheduling for MPSoCs via decomposition and no-good generation
IJCAI'05 Proceedings of the 19th international joint conference on Artificial intelligence
A general constraint-centric scheduling framework for spatial architectures
Proceedings of the 34th ACM SIGPLAN conference on Programming language design and implementation
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
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We present a decomposition strategy to speed up constraint optimization for a representative multiprocessor scheduling problem. In the manner of Benders decomposition, our technique solves relaxed versions of the problem and iteratively learns constraints to prune the solution space. Typical formulations suffer prohibitive run times even on medium-sized problems with less than 30 tasks. Our decomposition strategy enhances constraint optimization to robustly handle instances with over 100 tasks. Moreover, the extensibility of constraint formulations permits realistic application and resource constraints, which is a limitation of common heuristic methods for scheduling. The inherent extensibility, coupled with improved run times from a decomposition strategy, posit constraint optimization as a powerful tool for resource constrained scheduling and multiprocessor design space exploration.