The architecture of the DIVA processing-in-memory chip
ICS '02 Proceedings of the 16th international conference on Supercomputing
Gilgamesh: a multithreaded processor-in-memory architecture for petaflops computing
Proceedings of the 2002 ACM/IEEE conference on Supercomputing
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
Proceedings of the 30th annual international symposium on Computer architecture
Memory in processor: a novel design paradigm for supercomputing architectures
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Future generation supercomputers II: a paradigm for cluster architecture
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Future generation supercomputers II: a paradigm for cluster architecture
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
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As a result of the increasing requirements of present and future computation intensive applications, there have been many fundamentally divergent approaches such as the Blue-Gene, TRIPS, HERO, Cascade spurred in order to provide increased performance at node level in supercomputing clusters. The design of the node architecture should be such that 'Cost-Effective Supercomputing' is realized without compromising on the requirements of the ever-performance hungry grand challenge applications. However, to increase performance at the cluster level, scalability and likewise tackling the mapping complexity across the large cluster of nodes becomes critical. The potential of such a node architecture can be fully exploited only with an appropriate cluster architecture. In an attempt to address these issues for efficient and Cost-Effective Supercomputing, we propose a novel paradigm for designing High Performance Clusters, in two papers. In paper-II, we discuss the design of operating system and cluster architecture. In this paper, we present a node architecture model based on the Memory In Processor paradigm and discuss the related architectural aspects (ISA, compiler, network interconnection etc). We provide a design space based on the proposed model for which a simulator is developed, with the help of which the performance of such a node architecture is outlined.