Architecture-level performance evaluation of component-based embedded systems
Proceedings of the 40th annual Design Automation Conference
Performance Optimization by Wire and Buffer Sizing under the Transmission Line Model
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Efficient design space exploration of high performance embedded out-of-order processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Algorithms and analyses for maximal vector computation
The VLDB Journal — The International Journal on Very Large Data Bases
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A new rank correlation coefficient for information retrieval
Proceedings of the 31st annual international ACM SIGIR conference on Research and development in information retrieval
System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
On rank correlation and the distance between rankings
Proceedings of the 32nd international ACM SIGIR conference on Research and development in information retrieval
Rapid runtime estimation methods for pipelined MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
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Estimation models play a vital role in many aspects of day to day life. Extremely complex estimation models are employed in the design space exploration of SoCs, and the efficacy of these estimation models is usually measured by the absolute error of the models compared to known actual results. Such absolute error based metrics can often result in over-designed estimation models, with a number of researchers suggesting that fidelity of an estimation model (correlation between the ordering of the estimated points and the ordering of the actual points) should be examined instead of, or in addition to, the absolute error. In this paper, for the first time, we propose four metrics to measure the fidelity of an estimation model, in particular for use in design space exploration. The first two are based on two well known rank correlation coefficients. The other two are weighted versions of the first two metrics, to give importance to points nearer the Pareto front. The proposed fidelity metrics range from -1 to 1, where a value of 1 reflects a perfect positive correlation while a value of -1 reflects a perfect negative correlation. The proposed fidelity metrics were calculated for a single processor estimation model and a multiprocessor estimation model to observe their behavior, and were compared against the models' absolute error. For the multiprocessor estimation model, even though the worst average and maximum absolute error of 6.40% and 16.61% respectively can be considered reasonable in design automation, the worst fidelity of 0.753 suggests that the multiprocessor estimation model may not be as good a model (compared to an estimation model with same or higher absolute errors but a fidelity of 0.95) as depicted by its absolute accuracy, leading to an over-designed estimation model.