Performance estimation of embedded software with instruction cache modeling
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Hierarchical Scheduling and Allocation of Multirate Systems on Heterogeneous Multiprocessors
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Hardware/software co-synthesis with memory hierarchies
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Application-specific memory management for embedded systems using software-controlled caches
Proceedings of the 37th Annual Design Automation Conference
Code placement in hardware/software co-synthesis to improve performance and reduce cost
Proceedings of the conference on Design, automation and test in Europe
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Hardware/software co-synthesis with memory hierarchies
Readings in hardware/software co-design
Software-assisted cache replacement mechanisms for embedded systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Frequency-based code placement for embedded multiprocessors
Proceedings of the 42nd annual Design Automation Conference
Joint task assignment and cache partitioning with cache locking for WCET minimization on MPSoC
Journal of Parallel and Distributed Computing
Energy- and reliability-aware task scheduling onto heterogeneous MPSoC architectures
The Journal of Supercomputing
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This paper introduces the first high-level (task-level)model of hierarchical memories and describes a scheduling andallocation algorithm for system-level synthesis of heterogeneousmultiprocessors. Caches are essential for modern RISC embeddedcores to obtain sustained high performance. However, caches havereceived limited use in priority-driven preemptive real-time systemsdue to the unpredictability of caches-average-case improvementsare of no use in systems with hard deadlines. Program-levelcache models do not take into account preemptions between multipletasks running at multiple rates on embedded cores. Our task-levelmodel of performance in the presence of memory hierarchiesprovides an efficient means to bound the guaranteed memory performanceof tasks running in a multi-rate, multi-tasking environment.Our system synthesis algorithm uses software-based cachepartitioning and reservation techniques to guarantee cache hitsfor some tasks and therefore improve task schedulability. Experimentalresults show that our model significantly improves schedulabilityof real-time tasks and can be evaluated efficiently duringsystem-level synthesis.