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ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
A task-level hierarchical memory model for system synthesis of multiprocessors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
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Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
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ISSS '96 Proceedings of the 9th international symposium on System synthesis
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Multiprocessor embedded systems often have processor-local caches and a shared memory. If the system's code is available at design time we can maximize cache hits by rearranging code in memory so that frequently executed tasks reside in reserved areas of the caches and are not overwritten by less frequent tasks.