Improving IPC by kernel design
SOSP '93 Proceedings of the fourteenth ACM symposium on Operating systems principles
Communications of the ACM
Efficient microarchitecture modeling and path analysis for real-time software
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cost and Benefit of Separate Address Spaces in Real-Time Operating Systems
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
Worst-Case Execution Time Analysis of the RTEMS Real-Time Operating System
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
Chronos: A timing analyzer for embedded software
Science of Computer Programming
seL4: formal verification of an OS kernel
Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles
Improving interrupt response time in a verifiable protected microkernel
Proceedings of the 7th ACM european conference on Computer Systems
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Hard real-time systems are typically written to execute either on bare metal or on a small real-time executive that offers no memory protection. This model scales poorly as systems become more complex and integrated, as is the trend in industry today. Designing hard real-time systems on a protected OS is often avoided due to the difficulty in predicting its response time. Hard real-time systems with full virtual memory and memory protection have been proposed previously. However, to our knowledge, no such system has determined safe upper bounds on the latency introduced by this protection. This paper proposes that hard real-time systems can be constructed confidently and cost-effectively using an operating system providing full memory protection and virtual memory. We contend that a carefully written microkernel providing these mechanisms has the ability to be used in a hard real-time system without overly pessimistic response time guarantees. We use the seL4 microkernel as a case study, investigating how the features of seL4's design enable a highly accurate WCET analysis.